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1-314
High CMR Line Receiver
Optocouplers
Technical Data
HCPL-2602
HCPL-2612
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
Features
1000 V/
s Minimum Common
Mode Rejection (CMR) at
V
CM
= 50 V for HCPL-2602
and 3.5 kV/
s Minimum
CMR at V
CM
= 300 V for
HCPL-2612
Line Termination Included
No Extra Circuitry Required
Accepts a Broad Range of
Drive Conditions
LED Protection Minimizes
LED Efficiency Degradation
High Speed: 10 MBd
(Limited by Transmission
Line in Many Applications)
Guaranteed AC and DC
Performance over
Temperature: 0
C to 70
C
External Base Lead Allows
"LED Peaking" and LED
Current Adjustment
Safety Approval
UL Recognized 2500 V rms
for 1 Minute
CSA Approved
MIL-STD-1772 Version
Available (HCPL-1930/1)
A 0.1
F bypass capacitor must be connected between pins 5 and 8.
Applications
Isolated Line Receiver
Computer-Peripheral
Interface
Microprocessor System
Interface
Digital Isolation for A/D,
D/A Conversion
Current Sensing
Instrument Input/Output
Isolation
Ground Loop Elimination
Pulse Transformer
Replacement
Power Transistor Isolation
in Motor Drives
Description
The HCPL-2602/12 are optically
coupled line receivers that
combine a GaAsP light emitting
diode, an input current regulator
and an integrated high gain photo
detector. The input regulator
serves as a line termination for
line receiver applications. It
clamps the line voltage and
regulates the LED current so line
reflections do not interfere with
circuit performance.
The regulator allows a typical
LED current of 8.5 mA before it
starts to shunt excess current.
The output of the detector IC is
1
2
3
4
8
7
6
5
IN
IN+
GND
V
VCC
O
VE
NC
CATHODE
LED
ON
OFF
ON
OFF
ON
OFF
ENABLE
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
TRUTH TABLE
(POSITIVE LOGIC)
SHIELD
5965-3585E
1-315
Selection Guide
Widebody
Minimum CMR
8-Pin DIP (300 Mil)
Small-Outline SO-8
(400 Mil)
Hermetic
On-
Single
Dual
Single
Dual
Single
Single and
dV/dt
V
CM
Current
Output
Channel
Channel
Channel
Channel
Channel
Dual Channel
(V/
s)
(V)
(mA)
Enable
Package
Package
Package
Package
Package
Packages
NA
NA
5
YES
6N137
HCPL-0600
HCNW137
NO
HCPL-2630
HCPL-0630
5,000
50
YES
HCPL-2601
HCPL-0601
HCNW2601
NO
HCPL-2631
HCPL-0631
10,000
1,000
YES
HCPL-2611
HCPL-0611
HCNW2611
NO
HCPL-4661
HCPL-0661
1,000
50
YES
HCPL-2602
[1]
3,500
300
YES
HCPL-2612
[1]
1,000
50
3
YES
HCPL-261A
HCPL-061A
NO
HCPL-263A
HCPL-063A
1,000
[2]
1,000
YES
HCPL-261N
HCPL-061N
NO
HCPL-263N
HCPL-063N
1,000
50
12.5
[3]
HCPL-193X
HCPL-56XX
HCPL-66XX
Notes:
1. HCPL-2602/2612 devices include input current regulator.
2. 15 kV/
s with V
CM
= 1 kV can be achieved using HP application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
an open collector Schottky
clamped transistor. An enable
input gates the detector. The
internal detector shield provides a
guaranteed common mode
transient immunity specification
of 1000 V/
s for the 2602, and
3500 V/
s for the 2612.
DC specifications are defined
similar to TTL logic. The
optocoupler ac and dc operational
parameters are guaranteed from
0
C to 70
C allowing trouble-free
interfacing with digital logic
circuits. An input current of 5 mA
will sink an eight gate fan-out
(TTL) at the output.
The HCPL-2602/12 are useful as
line receivers in high noise
environments that conventional
line receivers cannot tolerate. The
higher LED threshold voltage
provides improved immunity to
differential noise and the internally
shielded detector provides orders
of magnitude improvement in
common mode rejection with little
or no sacrifice in speed.
Input
1-316
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-2602#XXX
300 = Gull Wing Surface Mount Option
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.
Schematic
SHIELD
8
6
5
2
4
VI
USE OF A 0.1 F BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS REQUIRED (SEE NOTE 1).
IF
ICC
VCC
VO
GND
IO
VE
IE
7
3
II
+
90
1-317
8-Pin DIP Package with Gull Wing Surface Mount Option 300
8-Pin DIP Package
Package Outline Drawings
9.65 0.25
(0.380 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
HP XXXX
YYWW
DATE CODE
1.080 0.320
(0.043 0.013)
2.54 0.25
(0.100 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
5
6
7
8
4
3
2
1
5 TYP.
TYPE NUMBER
UL
RECOGNITION
UR
0.254
+ 0.076
- 0.051
(0.010
+ 0.003)
- 0.002)
7.62 0.25
(0.300 0.010)
6.35 0.25
(0.250 0.010)
0.635 0.25
(0.025 0.010)
12 NOM.
9.65 0.25
(0.380 0.010)
0.635 0.130
(0.025 0.005)
7.62 0.25
(0.300 0.010)
5
6
7
8
4
3
2
1
9.65 0.25
(0.380 0.010)
6.350 0.25
(0.250 0.010)
1.016 (0.040)
1.194 (0.047)
1.194 (0.047)
1.778 (0.070)
9.398 (0.370)
9.906 (0.390)
4.826
(0.190)
TYP.
0.381 (0.015)
0.635 (0.025)
PAD LOCATION (FOR REFERENCE ONLY)
1.080 0.320
(0.043 0.013)
4.19
(0.165)
MAX.
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254
+ 0.076
- 0.051
(0.010
+ 0.003)
- 0.002)
1-318
Note: Use of nonchlorine activated fluxes is highly recommended.
240
T = 115C, 0.3C/SEC
0
T = 100C, 1.5C/SEC
T = 145C, 1C/SEC
TIME MINUTES
TEMPERATURE C
220
200
180
160
140
120
100
80
60
40
20
0
260
1
2
3
4
5
6
7
8
9
10
11
12
Solder Reflow Temperature Profile (Gull Wing Surface Mount Option 300 Parts)
Regulatory Information
The HCPL-2602/2612 have been
approved by the following
organizations:
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Min. External Air Gap
L(I01)
7.1
mm
Measured from input terminals to output terminals,
(External Clearance)
shortest distance through air.
Min. External Tracking
L(I02)
7.4
mm
Measured from input terminals to output terminals,
Path (External Creepage)
shortest distance path along body.
Min. Internal Plastic
0.08
mm
Through insulation distance, conductor to conductor,
Gap (Internal Clearance)
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity.
Tracking Resistance
CTI
200
V
DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-319
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level
I
IL
0
250
A
Input Current, High Level
I
IH
5*
60
mA
Supply Voltage, Output
V
CC
4.5
5.5
V
High Level Enable Voltage
V
EH
2.0
V
CC
V
Low Level Enable Voltage
V
EL
0
0.8
V
Fan Out (@ R
L
= 1 k
)
N
5
TTL Loads
Output Pull-up Resistor
R
L
330
4 K
Operating Temperature
T
A
0
70
C
*The initial switching threshold is 5 mA or less. It is recommended that an input current
between 6.3 mA and 10 mA be used to obtain best performance and to provide at least
20% LED degradation guardband.
Absolute Maximum Ratings
(No Derating Required up to 85
C)
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
T
S
-55
125
C
Operating Temperature
T
A
-40
85
C
Forward Input Current
I
I
60
mA
Reverse Input Current
I
IR
60
mA
Input Current, Pin 4
-10
10
mA
Supply Voltage (1 Minute Maximum)
V
CC
7
V
Enable Input Voltage (Not to Exceed V
CC
by
V
E
V
CC
+ 0.5
V
more than 500 mV)
Output Collector Current
I
O
50
mA
Output Collector Voltage (Selection for Higher
V
O
7
V
Output Voltages up to 20 V is Available.)
Output Collector Power Dissipation
P
O
40
mW
Lead Solder Temperature
T
LS
260
C for 10 sec., 1.6 mm below
seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings section
1-320
Electrical Characteristics
Over recommended temperature (T
A
= 0
C to +70
C) unless otherwise specified. See note 1.
Parameter
Sym.
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
High Level Output
I
OH
5.5
100
A
V
CC
= 5.5 V, V
O
= 5.5 V,
1
Current
I
I
= 250
A, V
E
= 2.0 V
Low Level Output
V
OL
0.35
0.6
V
V
CC
= 5.5 V, I
I
= 5 mA,
2, 4,
Voltage
V
E
= 2.0 V,
5, 14
I
OL
(Sinking) = 13 mA
High Level Supply
I
CCH
7.5
10
mA
V
CC
= 5.5 V, I
I
= 0 mA,
Current
V
E
= 0.5 V
Low Level Supply
I
CCL
10
13
mA
V
CC
= 5.5 V, I
I
= 60 mA,
Current
V
E
= 0.5 V
High Level Enable
I
EH
-0.7
-1.6
mA
V
CC
= 5.5 V, V
E
= 2.0 V
Current
Low Level Enable
I
EL
-0.9
-1.6
mA
V
CC
= 5.5 V, V
E
= 0.5 V
Current
High Level Enable
V
EH
2.0
V
10
Voltage
Low Level Enable
V
EL
0.8
V
Voltage
2.0
2.4
I
I
= 5 mA
Input Voltage
V
I
V
3
2.3
2.7
I
I
= 60 mA
Input Reverse
V
R
0.75
0.95
V
I
R
= 5 mA
Voltage
Input Capacitance
C
IN
90
pF
V
I
= 0 V, f = 1 MHz
*All typicals at V
CC
= 5 V, T
A
= 25
C.
1-321
Switching Specifications
Over recommended temperature (T
A
= 0
C to +70
C), V
CC
= 5 V, I
I
= 7.5 mA, unless otherwise specified.
Parameter
Symbol
Device
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay
75
ns
T
A
= 25
C
Time to High Output
t
PLH
20
48
6, 7, 8
3
Level
100
ns
Propagation Delay
75
ns
T
A
= 25
C
Time to Low Output
t
PHL
25
50
6, 7, 8
4
Level
100
ns
R
L
= 350
Pulse Width
|t
PHL
-t
PLH
|
3.5
35
ns
C
L
= 15 pF
9
13
Distortion
Propagation Delay
t
PSK
40
ns
12,
Skew
13
Output Rise Time
t
r
24
ns
12
(10-90%)
Output Fall Time
t
f
10
ns
12
(90-10%)
Propagation Delay
t
ELH
30
ns
R
L
= 350
, C
L
= 15 pF,
Time of Enable from
V
EL
= 0 V, V
EH
= 3 V
10, 11
5
V
EH
to V
EL
Propagation Delay
t
EHL
20
ns
R
L
= 350
, C
L
= 15 pF,
Time of Enable from
V
EL
= 0 V, V
EH
= 3 V
10, 11
6
V
EL
to V
EH
Common Mode
HCPL-2602
1000 10,000
V
CM
= 50 V
V
O(MIN)
= 2 V,
Transient
|CM
H
|
V/
s
R
L
= 350
,
13
7, 9,
Immunity at High
HCPL-2612
3500 15,000
V
CM
= 300 V
I
I
= 0 mA,
10
Output Level
T
A
= 25
C
Common Mode
HCPL-2602
1000 10,000
V
CM
= 50 V
V
O(MAX)
= 0.8 V,
Transient
|CM
L
|
V/
s
R
L
= 350
,
13
8, 9
Immunity at Low
HCPL-2612
3500 15,000
V
CM
= 300 V
I
I
= 7.5 mA,
10
Output Level
T
A
= 25
C
*All typicals at V
CC
= 5 V, T
A
= 25
C.
Package Characteristics
All Typicals at T
A
= 25
C
Parameter
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output Momentary
V
ISO
2500
V rms
RH
50%, t = 1 min.,
2, 11
Withstand Voltage
*
T
A
= 25
C
Input-Output Resistance
R
I-O
10
12
V
I-O
= 500 Vdc
2
Input-Output Capacitance
C
I-O
0.6
pF
f = 1 MHz
2
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or HP Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
1-322
7. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state
(i.e., V
OUT
> 2.0 V).
8. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e.,
V
OUT
< 0.8 V).
9. For sinusoidal voltages,
|dv
CM
|
=
f
CM
V
CM
(p-p)
dt
max
10. No external pull up is required for a high logic state on the enable input. If the V
E
pin is not used, tying V
E
to V
CC
will result in
improved CMR performance.
11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage of
3000 for one second
(leakage detection current limit, I
i-o
5
A).
12. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within the
operating condition range.
13. See application section titled "Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew" for more information.
Notes:
1. Bypassing of the power supply line is required, with a 0.1
F ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 15. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
2. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
3. The t
PLH
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising
edge of the output pulse.
4. The t
PHL
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling
edge of the output pulse.
5. The t
ELH
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point
on the rising edge of the output pulse.
6. The t
EHL
enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on
the falling edge of the output pulse.
Figure 1. Typical High Level Output
Current vs. Temperature.
Figure 2. Typical Low Level Output
Voltage vs. Temperature.
Figure 3. Typical Input Characteristics.
1.0
0
20
30
40
60
II INPUT CURRENT mA
10
50
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
V
I INPUT VOLTAGE V
25C
70C
0C
Figure 5. Typical Low Level Output
Current vs. Temperature.
Figure 4. Typical Output Voltage vs.
Forward Input Current.
1
6
2
3
4
5
1
2
3
4
5
6
IF FORWARD INPUT CURRENT mA
RL = 350
RL = 1 K
RL = 4 K
0
0
VCC = 5 V
TA = 25 C
V
O
OUTPUT VOLTAGE V
I OH
HIGH LEVEL OUTPUT CURRENT A
-60
0
TA TEMPERATURE C
100
10
15
-20
5
20
VCC = 5.5 V
VO = 5.5 V
VE = 2 V
II = 250 A
60
-40
0
40
80
VCC = 5.5 V
VE = 2 V
II = 5 mA
0.5
0.4
-60
-20
20
60
100
TA TEMPERATURE C
0.3
80
40
0
-40
0.1
V
OL
LOW LEVEL OUTPUT VOLTAGE V
0.2
IO = 16 mA
IO = 12.8 mA
IO = 9.6 mA
IO = 6.4 mA
VCC = 5 V
VE = 2 V
VOL = 0.6 V
70
60
-60
-20
20
60
100
TA TEMPERATURE C
50
80
40
0
-40
20
I OL
LOW LEVEL OUTPUT CURRENT mA
40
II = 10-15 mA
II = 5.0 mA
1-323
Figure 10. Test Circuit for t
EHL
and t
ELH
.
Figure 11. Typical Enable Propagation
Delay vs. Temperature.
Figure 7. Typical Propagation Delay
vs. Temperature.
Figure 8. Typical Propagation Delay
vs. Pulse Input Current.
Figure 9. Typical Pulse Width
Distortion vs. Temperature.
Figure 6. Test Circuit for t
PHL
and t
PLH
.
OUTPUT V
MONITORING
NODE
O
+5 V
7
5
6
8
2
3
4
1
PULSE GEN.
Z = 50
t = t = 5 ns
O
f
I I
L
R
RM
CC
V
0.1F
BYPASS
*CL
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
GND
INPUT
MONITORING
NODE
r
1.5 V
t
PHL
t
PLH
I
I
INPUT
O
V
OUTPUT
I = 7.50 mA
I
I = 3.75 mA
I
VCC = 5 V
II = 7.5 mA
100
80
-60
-20
20
60
100
TA TEMPERATURE C
60
80
40
0
-40
0
t P
PROPAGATION DELAY ns
40
20
tPLH , RL = 4 K
tPLH , RL = 1 K
tPLH , RL = 350
tPHL , RL = 350
1 K
4 K
VCC = 5 V
TA = 25C
105
90
5
9
13
II PULSE INPUT CURRENT mA
75
15
11
7
30
t P
PROPAGATION DELAY ns
60
45
tPLH , RL = 4 K
tPLH , RL = 1 K
tPLH , RL = 350
tPHL , RL = 350
1 K
4 K
VCC = 5 V
II = 7.5 mA
40
30
-20
20
60
100
TA TEMPERATURE C
20
80
40
0
-40
PWD PULSE WIDTH DISTORTION ns
10
RL = 350 k
RL = 1 k
RL = 4 k
0
-60
-10
OUTPUT V
MONITORING
NODE
O
1.5 V
tEHL
tELH
VE
INPUT
O
V
OUTPUT
3.0 V
1.5 V
+5 V
7
5
6
8
2
3
4
1
PULSE GEN.
Z = 50
t = t = 5 ns
O
f
I I
L
R
CC
V
0.1 F
BYPASS
*CL
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
GND
r
7.5 mA
INPUT VE
MONITORING NODE
t E
ENABLE PROPAGATION DELAY ns
-60
0
TA TEMPERATURE C
100
90
120
-20
30
20
60
-40
0
40
80
60
VCC = 5 V
VEH = 3 V
VEL = 0 V
II = 7.5 mA
tELH, RL = 4 k
tELH, RL = 1 k
tEHL, RL = 350
,
1
k
,
4 k
tELH, RL = 350
1-324
GND BUS (BACK)
V
CC
BUS (FRONT)
ENABLE
(IF USED)
0.1F
OUTPUT 1
NC
NC
ENABLE
(IF USED)
0.1F
OUTPUT 2
NC
NC
10 mm MAX.
(SEE NOTE 1)
Figure 13. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms.
Figure 12. Typical Rise and Fall Time
vs. Temperature.
t r
, t
f RISE, FALL TIME ns
-60
0
TA TEMPERATURE C
100
300
-20
40
20
60
-40
0
40
80
60
290
20
VCC = 5 V
II = 7.5 mA
RL = 4 k
RL = 1 k
RL = 350
,
1 k
, 4 k
tRISE
tFALL
RL = 350
+5 V
7
5
6
8
2
3
4
1
CC
V
0.1 F
BYPASS
GND
OUTPUT V
MONITORING
NODE
O
PULSE
GENERATOR
Z = 50
O
+
I I
B
A
CM
V
350
VO
0.5 V
O
V (MIN.)
5 V
0 V
SWITCH AT A: I = 0 mA
I
SWITCH AT B: I = 7.5 mA
I
CM
V
H
CM
CML
O
V (MAX.)
CM
V (PEAK)
VO
Figure 15. Recommended Printed Circuit Board Layout.
Figure 14. Typical Input Threshold
Current vs. Temperature.
I TH
INPUT THRESHOLD CURRENT mA
-60
0
TA TEMPERATURE C
100
4
5
-20
2
20
60
-40
0
40
80
3
VCC = 5.0 V
VO = 0.6 V
1
RL = 4 k
RL = 1 k
RL = 350
1-325
Using the HCPL-2602/12
Line Receiver
Optocouplers
The primary objectives to fulfill
when connecting an optocoupler
to a transmission line are to
provide a minimum, but not
excessive, LED current and to
properly terminate the line. The
internal regulator in the HCPL-
2602/12 simplifies this task.
Excess current from variable drive
conditions such as line length
variations, line driver differences,
and power supply fluctuations are
shunted by the regulator. In fact,
with the LED current regulated,
the line current can be increased
to improve the immunity of the
system to differential-mode-noise
and to enhance the data rate
capability. The designer must
keep in mind the 60 mA input
current maximum rating of the
HCPL-2602/12 in such cases, and
may need to use series limiting or
shunting to prevent overstress.
Design of the termination circuit
is also simplified; in most cases
the transmission line can simply
be connected directly to the input
terminals of the HCPL-2602/12
without the need for additional
series or shunt resistors. If
reversing line drive is used it may
be desirable to use two HCPL-
2602/12 or an external Schottky
diode to optimize data rate.
Polarity Non-Reversing
Drive
High data rates can be obtained
with the HCPL-2602/12 with
polarity non-reversing drive.
Figure (a) illustrates how a
74S140 line driver can be used
with the HCPL-2602/12 and
shielded, twisted pair or coax
cable without any additional
components. There are some
reflections due to the "active
termination," but they do not
interfere with circuit performance
because the regulator clamps the
line voltage. At longer line
lengths, t
PLH
increases faster than
t
PHL
since the switching threshold
is not exactly halfway between
asymptotic line conditions. If
optimum data rate is desired, a
series resistor and peaking
capacitor can be used to equalize
t
PLH
and t
PHL
. In general, the
peaking capacitance should be as
large as possible; however, if it is
too large it may keep the regulator
from achieving turn-off during the
negative (or zero) excursions of
the input signal. A safe rule:
make C
16t
where:
C = peaking capacitance in
picofarads
t = data bit interval in
nanoseconds
Polarity Reversing Drive
A single HCPL-2602/12 can also
be used with polarity reversing
drive (Figure b). Current reversal
is obtained by way of the
substrate isolation diode
(substrate to collector). Some
reduction of data rate occurs,
however, because the substrate
diode stores charge, which must
be removed when the current
changes to the forward direction.
The effect of this is a longer t
PHL
.
This effect can be eliminated and
data rate improved considerably
by use of a Schottky diode on the
input of the HCPL-2602/12.
For optimum noise rejection as
well as balanced delays, a split-
phase termination should be used
along with a flip-flop at the
output (Figure c). The result of
current reversal in split-phase
operation is seen in Figure (c)
with switches A and B both
OPEN. The coupler inputs are
then connected in ANTI-SERIES;
however, because of the higher
steady-state termination voltage,
in comparison to the single
HCPL-2602/12 termination, the
forward current in the substrate
diode is lower and consequently
there is less junction charge to
deal with when switching.
Closing switch B with A open is
done mainly to enhance common
mode rejection, but also reduces
propagation delay slightly
because line-to-line capacitance
offers a slight peaking effect.
With switches A and B both
CLOSED, the shield acts as a
current return path which
prevents either input substrate
diode from becoming reversed
biased. Thus the data rate is
optimized as shown in Figure (c).
Improved Noise Rejection
Use of additional logic at the
output of two HCPL-2602/12s,
operated in the split phase
termination, will greatly improve
system noise rejection in addition
to balancing propagation delays
as discussed earlier.
A NAND flip-flop offers infinite
common mode rejection (CMR)
for NEGATIVELY sloped common
mode transients but requires t
PHL
> t
PLH
for proper operation. A
NOR flip-flop has infinite CMR for
POSITIVELY sloped transients
but requires t
PHL
< t
PLH
for proper
operation. An exclusive-OR flip-
flop has infinite CMR for common
mode transients of EITHER
polarity and operates with either
t
PHL
> t
PLH
or t
PHL
< t
PLH
.
With the line driver and
transmission line shown in Figure
(c), t
PHL
> t
PLH
, so NAND gates are
preferred in the R-S flip-flop. A
higher drive amplitude or
1-326
Figure b. Polarity Reversing, Single Ended.
Figure a. Polarity Non-Reversing.
Figure c. Polarity Reversing, Split Phase.
Figure d. Flip-Flop Configurations.
< 1
< 1
1-327
different circuit configuration
could make t
PHL
< t
PLH
, in which
case NOR gates would be pre-
ferred. If it is not known whether
t
PHL
> t
PLH
or t
PHL
< t
PLH
, or if the
drive conditions may vary over
the boundary for these conditions,
the exclusive-OR flip-flop of
Figure (d) should be used.
RS-422 and RS-423
Line drivers designed for RS-422
and RS-423 generally provide
adequate voltage and current for
operating the HCPL-2602/12.
Most drivers also have
characteristics allowing the
HCPL-2602/12 to be connected
directly to the driver terminals.
Worst case drive conditions,
however, would require current
shunting to prevent overstress of
the HCPL-2602/12.
Propagation Delay, Pulse-
Width Distortion and
Propagation Delay Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high (t
PLH
)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (t
PHL
) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low (see
Figure 6).
Pulse-width distortion (PWD)
results when t
PLH
and t
PHL
differ in
value. PWD is defined as the
difference between t
PLH
and t
PHL
and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being
transmitted. Typically, PWD on
the order of 20-30% of the
minimum pulse width is tolerable;
the exact figure depends on the
particular application (RS232,
RS422, T-1, etc.).
Propagation delay skew, t
PSK
, is an
important parameter to consider
in parallel data applications where
synchronization of signals on
parallel data lines is a concern. If
the parallel data is being sent
through a group of optocouplers,
differences in propagation delays
will cause the data to arrive at the
outputs of the optocouplers at
different times. If this difference
in propagation delays is large
enough, it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Propagation delay skew is defined
as the difference between the
minimum and maximum
propagation delays, either t
PLH
or
t
PHL
, for any given group of
optocouplers which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and
operating temperature). As
illustrated in Figure 16, if the
inputs of a group of optocouplers
are switched either ON or OFF at
the same time, t
PSK
is the
difference between the shortest
propagation delay, either t
PHL
or
t
PHL
, and the longest propagation
delay, either t
PLH
or t
PHL
.
As mentioned earlier, t
PSK
can
determine the maximum parallel
data transmission rate. Figure 17
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
Propagation delay skew
represents the uncertainty of
where an edge might be after
being sent through an
optocoupler. Figure 17 shows
that there will be uncertainty in
both the data and the clock lines.
It is important that these two
areas of uncertainty not overlap,
otherwise the clock signal might
arrive before all of the data
outputs have settled, or some of
the data outputs may start to
change before the clock signal
has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice t
PSK
. A
cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
The t
PSK
specified optocouplers
offer the advantages of
guaranteed specifications for
propagation delays, pulse-width
distortion and propagation delay
skew over the recommended
temperature, input current, and
power supply ranges.
1-328
Figure 16. Illustration of Propagation Delay Skew -
t
PSK
.
Figure 17. Parallel Data Transmission Example.
DATA
t
PSK
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
50%
1.5 V
I I
VO
50%
I I
VO
tPSK
1.5 V
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